1. Field of the Invention
The present invention relates to a semiconductor memory device such as SDRAM (Synchronous Dynamic Random Access Memory), and more particularly to a semiconductor memory device that uses capacitor fuses to effect a one-bit remedy, and to a method of remedying a defective cell.
2. Description of the Related Art
Semiconductor memory devices such as DRAM are provided with a large number of memory cells, and it is therefore inevitable that some memory cells will be defective memory cells, i.e., cells that do not function properly. Discarding the entire semiconductor memory device as a defective product when such a defective memory cell occurs increases the cost of fabricating the semiconductor memory device, and various methods have therefore been proposed as methods of remedying defective cells that occur.
When a defective cell is discovered in an investigation of a semiconductor memory device in the wafer state, the defective cell is replaced by a redundant cell that has been prepared in advance to maintain the overall integrity of the semiconductor memory device. To effect this replacement, it is necessary to store the address of the defective cell, and fuse elements are used to store the address of this defective cell. Fuse elements include elements that normally function as resistor elements but that blow out upon the flow of an overcurrent and thus enter an insulating state, and elements that are cut by the irradiation of a laser beam.
However, because the formation of a resistor element requires a certain amount of surface area, the use of these resistor elements as fuse elements raises the problem of increase in the layout area with increase in the number of fuse elements that are used. On the other hand, once a semiconductor memory device has been packaged, a laser beam cannot be irradiated to cut the fuse elements.
Capacitor fuses are therefore used for remedying defective cells that are discovered after packaging. A capacitor fuse is an element in which the application of a high voltage across two electrodes that are normally in an insulating state can bring about a dielectric breakdown that destroys a dielectric film and thus place the two electrodes in a connected state. By using such a capacitor fuse, one fuse element can be realized in the same layout area that is required for one memory cell. In addition, cutting of a capacitor fuse requires only the application of a high voltage to the capacitor fuse, and it is therefore possible to cut a capacitor fuse after a semiconductor memory device has been packaged.
In contrast to a normal fuse element, which functions as a resistor element before cutting and then enters an open state after cutting, a capacitor fuse functions as a capacitor with an open state established between two terminals before cutting and then functions as a resistor element after cutting.
As a method of remedying defective cells after a semiconductor memory device has been packaged, a method has been proposed in recent years that uses a one-bit remedy employing the above-described capacitor fuse. When a defective cell is discovered after a semiconductor memory device has been packaged, this one-bit remedy method stores the data that was to be stored in the defective cell in a storage circuit such as a latch circuit.
In this one-bit remedy, the discovery of a defective cell does not result in the separate storage of only the data that are stored in the defective cell. Instead, a unit of cells that are activated by a column selection circuit (Y-switch circuit) are taken as the unit of simultaneous remedy, and all of the data that are stored in all memory cells that are included in this simultaneous remedy unit are separately stored.
FIG. 1 shows the construction of a semiconductor memory device of the prior art that effects this type of one-bit remedy. As shown in FIG. 1, this semiconductor memory device of the prior art is provided with memory cell array 10 that is composed of a plurality of memory cells, row decoder 20, column decoder 30, comparison circuit 40, address buffer circuit 150, and capacitor fuse blocks 801-80n.
An external address signal that is used in, for example DRAM, is composed of alternately arranged row addresses and column addresses. As a result, address buffer circuit 150 not only divides external address signal 1 that is applied from outside the semiconductor memory device into row address signal 2 and column address signal 3, but also holds row address signal 2 and column address signal 3 until external address signal 1 designates the next address.
FIG. 2 shows a specific composition of this address buffer circuit 150. As shown in FIG. 2, address buffer circuit 150 is provided with inverter circuits 51, 52, 55-57, 58, 59, 62-64, 86, and 87; p-channel MOS transistors 53 and 60; and n-channel MOS transistors 54 and 61. This composition that is shown in FIG. 2 is for a one-bit portion of the address signal, and in an actual address buffer circuit, the circuit structure that is shown in FIG. 2 is provided in a number equal to the number of bits of the address signal.
In addition, row address latch signal 5 and column address latch signal 6 are applied as input to this address buffer circuit 150 as shown in FIG. 1, and when external address signal 1 indicates a row address, row address latch signal 5 becomes high level for a fixed interval; and when external address signal 1 indicates a column address, column address latch signal 6 becomes high level for a fixed interval.
Inverter circuits 86 and 87 invert row address latch signal 5 and column address latch signal 6, respectively, and supply the result as output. Inverter circuits 51 and 58 invert external address signal 1 and supply the result as output. Inverter circuit 52 inverts the output of inverter circuit 86 and supplies the result to the gate of n-channel MOS transistor 54. Inverter circuit 59 inverts the output of inverter circuit 87 and supplies the result to the gate of n-channel MOS transistor 61.
P-channel MOS transistor 53 receives the output of inverter circuit 86 at its gate, turns on when row address latch signal 5 becomes high level and the output of inverter circuit 86 becomes low level, and supplies the output of inverter circuit 51 to data holding unit that is composed of inverter circuits 55 and 56. N-channel MOS transistor 54 receives the output of inverter circuit 52 at its gate, and, as with p-channel MOS transistor 53, turns on when row address latch signal 5 becomes high level and supplies the output of inverter circuit 51 to a data holding unit that is composed of inverter circuits 55 and 56.
Inverter circuits 55 and 56 each invert the output of the other and thus hold signals that are transmitted by way of p-channel MOS transistor 53 and n-channel MOS transistor 54. Inverter circuit 57 inverts the value that is held by inverter circuits 55 and 56 and supplies the result as row address signal 2.
P-channel MOS transistor 60 receives the output of inverter circuit 87 at its gate, turns on when column address latch signal 6 becomes high level and the output of inverter circuit 87 becomes low level, and supplies the output of inverter circuit 58 to the data holding unit that is composed of inverter circuits 62 and 63. N-channel MOS transistor 61 receives the output of inverter circuit 59 at its gate, and, similar to p-channel MOS transistor 60, turns on when column address latch signal 6 becomes high level and supplies the output of inverter circuit 58 to the data holding unit that is composed of inverter circuits 62 and 63.
Inverter circuits 62 and 63 each invert the output of the other and thereby hold the signal that is transmitted by way of p-channel MOS transistor 60 and n-channel MOS transistor 61. Inverter circuit 64 inverts the value that is held by inverter circuits 62 and 63 and supplies the result as column address signal 3.
According to the above-described construction of address buffer circuit 150, the change of row address latch signal 5 to high level causes the row address that is contained in external address signal 1 to be latched and supplied as row address signal 2; and the change of column address latch signal 6 to high level causes the column address that is contained in external address signal 1 to be latched and supplied as column address signal 3.
Row decoder 20 that is shown in FIG. 1 activates the word line that is designated by row address signal 2 from address buffer circuit 150. Column decoder 30 activates the column selection signal that is designated by column address signal 3 from address buffer circuit 150 and connects the bit line with the I/O bus.
Comparison circuit 40 that is shown in FIG. 1 is a circuit that operates when the semiconductor memory device is to be checked. This comparison circuit 40 reads, to outside the memory cell array by way of the I/O bus, the data of bit lines that are selected by the plurality of column selection signals that have been selected simultaneously by column decoder 30, compares this data to determine whether defective cells are present in memory cell array 10, and supplies the determination results as determination signal 4.
For example, when memory cell array 10 that is shown in FIG. 1 is provided with 16 I/O buses, an I/O compression test is carried out by a method such as shown in FIG. 3a. 
In FIG. 3a, the data that are represented by the solid lines, dotted lines, broken lines, and dot-and-dash lines are each different, but data that are represented by the same type of line are identical. The data from this memory cell array 10 are applied to comparison circuit 40 by way of data amplifiers 32 and subjected to an I/O compression test.
An actual example of the construction of comparison circuit 40 for carrying out this type of I/O compression test is shown in the circuit diagram of FIG. 3b. 
As shown in FIG. 3b, this comparison circuit 40 is composed of four determination blocks 411-414, NAND circuits 42, 44, and 45, and inverter circuit 43.
The sixteen items of data that are applied as input to comparison circuit 40 are each arranged in groups of data that should be the same and then applied as input to a respective block of four determination blocks 411-414.
Determination block 411 is composed of NAND circuit 46, NOR circuits 47 and 49, and inverter circuits 48 and 31. NAND circuit 46 inverts the calculated logical product of the four items of data that are applied as input to determination block 411, and supplies the result as output. Inverter circuit 48 inverts the output of NAND circuit 46 and supplies the result as output. NOR circuit 47 inverts the calculated logical sum of the four items of data that are applied as input to determination block 411 and supplies the result as output. NOR circuit 49 then inverts the result of calculating the logical sum of the output from inverter circuit 48 and the output of NOR circuit 47 and supplies the result as output. Inverter circuit 31 then inverts the output of NOR circuit 49 and supplies the result as output to NAND circuit 42.
According to the above-described construction, determination block 411 supplies a high-level signal when the four signals that have been applied as input are all high level or are all low level, and otherwise supplies a low-level signal. Determination blocks 412-414 have the same construction and operation as determination block 411, and redundant explanation of these blocks is therefore omitted.
NAND circuit 42 inverts the result of calculating the logical product of the signals from four determination blocks 411-414 and supplies the result as output. Inverter circuit 43 inverts the output of NAND circuit 42 and supplies the result as output. NAND circuit 44 and 45, which form a latch circuit, latch and invert the output of inverter circuit 43, and supply the result as output.
Determination reset signal 12 is applied as input to NAND circuit 45 that forms a portion of this latch circuit. This determination reset signal 12 is used when the power supply is introduced or when rechecking. This signal is normally low level, and the change of the signal from low level to high level sets determination signal 4 to low level.
As an example, when the four items of data that are supplied to determination block 411 are all high level, the output of NAND circuit 46 becomes low level, and the output of inverter circuit 48 becomes high level. As a result, the output of NOR circuit 49 becomes low level, and the output of inverter circuit 31 becomes high level.
When no defective cells are present within the range of simultaneous remedy that is the object of a check, the output from all four determination blocks 411-414 are all high level, the output of NAND circuit 42 becomes low level, and the output of inverter circuit 43 becomes high level. In this case, determination reset signal 12 is normally low level, and determination signal 4 becomes low level, indicating that there are no defective cells.
The existence of defective cells within memory cell array 10 is detected by carrying out the above-described check while changing the row addresses and column addresses for every unit of simultaneous remedy. When a defective cell is present within the object of checking, the output of any one of four determination blocks 411-414 becomes low level, whereby the output of NAND circuit 42 becomes high level and the output of inverter circuit 43 becomes low level. Determination signal 4 thus becomes high level, thereby indicating the existence of a defective cell.
Capacitor fuse blocks 801-80n are each composed of a plurality of capacitor fuses for storing the row address and column address of a defective cell, and when cut mode signal 11 becomes high level, each capacitor fuse is cut based on the address of the defective cell that is indicated by capacitor fuse address signal 9.
We next refer to FIG. 4 to explain the one-bit remedy operation. The circuit diagram on the left side of FIG. 4 is the circuit diagram for writing data, and the circuit diagram on the right side of FIG. 4 is the circuit diagram for reading data.
In this case, defective cell address detection signal 15 is a signal that becomes high level when the external address signal matches the address of a defective cell that has been programmed into the fuse block in advance. Write amplifier activation signal 13 is a signal that becomes high level when data are to be written, and data amplifier activation signal 14 is a signal that becomes high level when data are to be read.
Explanation first regards the operation for writing data. When external address signal matches with an address that has been programmed into a fuse block and defective cell address detection signal 15 becomes high level, write amplifier activation signal 13 is already high level when data are being written, and the output of NAND circuit 72 therefore becomes low level and p-channel MOS transistor 75 turns on. In addition, the change to low level of the output of NAND circuit 72 causes the output of inverter circuit 73 to become high level and n-channel MOS transistor 74 therefore turns on. As a result, the write data that are received as input at this time are held in inverter circuits 76 and 77.
Explanation next regards the operations for reading data. When defective cell address detection signal 15 is at low level, the output of NAND circuit 79 becomes high level and the output of inverter circuit 81 becomes low level. As a result, the output of NAND circuit 82 becomes high level, the output of NOR circuit 83 becomes high level, and p-channel MOS transistor 84 and n-channel MOS transistor 85 both turn off. In this case, when defective cell address detection signal 15 becomes high level, the output of NAND circuit 79 becomes low level and the output of inverter circuit 81 becomes high level. As a result, the value that is obtained when inverter circuit 78 inverts the value that is held by inverter circuits 76 and 77 is applied as input to NAND circuit 82 and NOR circuit 83. When high-level write data are being held, p-channel MOS transistor 84 turns on and a high-level value is supplied as the read data. Alternatively, when low-level write data are being held, n-channel MOS transistor 85 turns on and a low-level value is supplied as the read data.
We next refer to the flow chart of FIG. 5 to explain the method of remedying defective cells when in the process of fabricating a prior-art semiconductor memory device of this type. When carrying out packaging in the fabrication process of a semiconductor memory device, an I/O compression test is first carried out in step 201 as previously described to determine whether defective cells are present. If no defective cells are found in the I/O compression test and an xe2x80x9cOKxe2x80x9d is determined in step 201, tests of the various functions are carried out in step 204 and, if the product passes all of the tests, the product is determined to be satisfactory. If a problem is discovered in the function tests of step 204, the product is determined to be defective.
If a defective cell is discovered in the I/O compression test in step 201 and xe2x80x9cNGxe2x80x9d is determined, the identity of the defective cell is next checked in step 202. Then, in step 203, the address of this defective cell is stored by cutting capacitor fuses in order to effect a one-bit remedy. After cutting the capacitor fuses, function tests are carried out in step 204 just as if an xe2x80x9cOKxe2x80x9d had been determined in the I/O compression test in step 201.
In the method of remedying a defective cell that was described using FIG. 5, two selection steps are provided in the form of an I/O compression test and function tests. Although this I/O compression test is a simple test, the function tests are more detailed tests that include the I/O compression test. Two selection steps are provided in the form of a simple test and a more detailed test because the discovery of a problem after carrying out various tests and the resulting remedy such as a one-bit remedy would necessitate the repeat of all tests from the very start, making all preceding tests pointless. In other words, the ability to detect a problem by means of a simple test can eliminate the time and effort that would be lost in performing other unnecessary tests.
In the remedy method of the prior art that is shown in FIG. 5, a semiconductor memory device that has been determined to be xe2x80x9cNGxe2x80x9d in the I/O compression test of step 201 is first removed from the fabrication process, following which the defective cell addresses are identified (step 202) and the capacitor fuses cut (step 203) outside the fabrication process. In addition, when identifying the addresses of defective cells, a tester with a fail memory is used that is provided with the capacity for detecting and storing defective cell addresses. However, this tester having a fail memory is more expensive than a tester that detects only the existence of defective cells, and including a tester having a fail memory in a mass production process would therefore increase the costs of fabricating the semiconductor memory devices. In addition, the determination of xe2x80x9cNGxe2x80x9d in the I/O compression test necessitates further checking of all of the memory cells, the determination of the addresses of defective cells, and the cutting of capacitor fuses, all these steps being above and beyond the normal fabrication process, and thus raises the problems of not only increasing the time and effort expended in the test process but greatly complicating the test process. Finally, the need to provide an expensive tester having a fail memory in a mass production process entails the further problem of increasing costs of plant and equipment investment.
It is an object of the present invention to provide a semiconductor memory device and a method for remedying defective cells that can not only simplify the test process by eliminating the time and effort that is above and beyond the fabrication process, but also limit investment in equipment by eliminating the need for a tester having a fail memory.
To achieve the above-described object, the semiconductor memory device of the present invention is provided with a comparison circuit, an address buffer circuit, and a capacitor fuse block.
The comparison circuit compares a plurality of data that have been simultaneously read from a memory cell array in a test process for checking for the presence of defective cells to determine whether a defective cell exists in the memory cell array and supplies the determination result as a determination signal.
The address buffer circuit splits an external address signal into row addresses and column addresses and supplies the result as output, and further, upon input of a determination signal from the comparison circuit, latches the row address and column address that are being supplied at that time and supplies the latched row address and column address as the capacitor fuse address for cutting capacitor fuses.
The capacitor fuse block is composed of a plurality of capacitor fuses and effects the cutting of each of the capacitor fuse elements based on capacitor fuse addresses that have been latched by the address buffer circuit.
In addition, as a test for checking for the existence of defective cells in a semiconductor memory device of the present invention, the comparison circuit may perform an I/O compression test for detecting the existence of defective cells by comparing data that have been read from memory cells within a simultaneous remedy range in which a one-bit remedy is effected.
According to the present invention, when a defective cell has been detected in a test process for checking for the existence of defective cells, the address buffer circuit latches the row address and column address at the time the defective cell was detected and supplies the row address and column address as a capacitor fuse address; and the capacitor fuse block then cuts each capacitor fuse based on this capacitor fuse address. Accordingly, cutting of capacitor fuses can be carried out automatically as a part of the fabrication process and the need for detecting the address of a defective cell outside the fabrication process can be eliminated. The present invention can also eliminate the expense of time and effort outside the fabrication process, can simplify the test process, and finally, by eliminating the need for a tester having a fail memory, can limit investment in equipment.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings, which illustrate examples of the present invention.